Leakage Power Reduction in Cmos Circuits Using Leakage Control Transistor Technique in Nanoscale Technology
نویسندگان
چکیده
In this paper, we propose a leakage reduction technique. Because high leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits. Sub threshold leakage current plays a very important role in power dissipation. So to reduce the sub threshold leakage current we proposed an adaptive voltage level (AVL) technique. Which optimize the overall voltage across the half subtractor circuit in active mode. In this AVL technique, Two schemes are employed, one is AVLS (adaptive voltage level at supply) in which the supply voltage is reduced and the other is AVLG (adaptive voltage level at ground) in which the ground potential is increased. By applying this technique we have reduced the leakage current from 9.274pa to 5.428. That means this technique the leakage current 41.4% .the circuit is simulated on cadence virtuoso in 45nm CMOS technology. Simulation results revealed that there is a significant reduction in leakage current for this proposed cell with the AVL circuit reducing the supply voltage.
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Leakage Power Reduction in Cmos Circuits Using Leakage Control Transistor Technique in Nanoscale Technology
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